Calculating the effect of inductance on the time required to propagate voltage swings through the interconnect wiring of an integrated circuit is complex and time consuming. For example, return paths are required to accurately model the inductive effects. Moreover, extraction of inductance on large designs is difficult, time consuming and memory intensive. As such, inductance extraction is often ignored. However, with technologies getting faster and frequencies increasing, ignoring the effect of inductance may lead to inaccuracies, and can lead to incorrect results.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove, to provide a fast estimate of the effect of inductance on timing.